 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Features w w * High-speed (HS) Programmable Serial InterfaceTM (PSITM) * 2.48- to 2.5-Gbps serial signaling rate * Full Bellcore and ITU jitter compliance * Flexible parallel-to-serial conversion in transmit path * Flexible serial-to-parallel conversion in receive path * Multiple selectable loopback/loop-through modes * 100K of usable gates of CPLD logic * 240K of integrated memory -- 192K of synchronous or asynchronous SRAM w .D at Sh a et e 4U . om c 2.5-Gbps Programmable Serial InterfaceTM -- Circuit board traces -- Backplane links -- Box-to-box links -- Chip-to-chip communication * Extremely flexible clocking options -- Four global clocks -- Up to 192 additional product term clocks -- Clock polarity at every register * Carry chain logic for fast and efficient arithmetic operations * JTAG programming interface with boundary scan support * Power-saving mode * Supported standards: -- SONET OC-48 and SDH STM-16 -- InfiniBandTM -- Custom 2.5-Gbps interface * * * * * * * * -- 48K of true Dual-Port or FIFO RAM Internal transmit and receive phase-locked loops (PLLs) Logic dedicated Spread Aware PLL Transmit FIFO for flexible variable phase clocking Differential CML serial input with internal termination and DC-restoration Differential CML serial output with source-matched impedance of 50 240 user-programmable I/Os Any VoltTM I/O interface -- Programmable as 1.5V, 1.8V, 2.5V, 3.3V Multiple I/O standards -- LVCMOS, LVTTL, 3.3V PCI, SSTL2(I-II), SSTL3(I-II), HSTL(I-IV), and GTL+ -- Fully PCI-compliant (Rev. 2.2) * Direct interface to standard fiber-optic modules * Designed to drive: -- Fiberoptic modules -- Copper cables 2.5-Gbps PSI Family--Standards Supported PSI Device SONET/SDH High Speed CYS25G01K100 CYP25G01K100 2.5-Gbps PSI Family--General Features Device Typical Gates Macrocells 1536 Cluster Memory (Kbits) 192 Channel Memory (Kbits) 48 Maximum UserProgrammable I/O 240 Package Offering w w w .D t a S a X e h Development Software * Warp(R) -- IEEE 1076/1164 VHDL or IEEE 1364 Verilog context sensitive editing -- Active-HDL FSM graphical finite state machine editor -- Active-HDL SIM post-synthesis timing simulator -- Architecture Explorer for detailed design analysis -- Static Timing Analyzer for critical path analysis -- Available on Windows(R) 9x, 2000, NT 4.0, XP, and ME -- Supports all Cypress programmable logic products t e U 4 .c m o SONET/SDH (OC48/STM16) InfiniBand X Custom X X 25G01K100 46K-144K 456-BGA (35 x 35 mm, 1.27-mm pitch) 2.5-Gbps PSI Family--Performance Device 25G01K100 Channels and Link Speed 1 x 2.5 Gbps Total Bandwidth 2.5 Gbps fMAX2(Logic)[1] (MHz) 222 Note: 1. See the section titled Switching Characteristics for definition. Cypress Semiconductor Corporation Document #: 38-02021 Rev. *C * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised December 4, 2002 w w w .D at Sh a et e 7.5 4U . om c Logic Speed-- tPD Pin-to-Pin[1] (ns) 2.5-Gbps Programmable Serial Interface GCLK[1:0] RXCLK TXCLK PLL & Clock MUX GCTL[3:0] 4 4 GCLK[1:0], RXCLK, TXCLK 4 I/O Bank 4 4 I/O Bank 4 LB 0 LB 1 LB 2 LB 3 Cluster RAM LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM GCLK[1:0], RXCLK, TXCLK 4 4 4 4 I/O Bank LB 1 LB 2 LB 3 Cluster RAM LB 6 LB 1 LB 6 LB 1 LB 6 LB 1 LB 6 PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM GCLK[1:0], RXCLK, TXCLK 4 4 4 4 I/O Bank LB 0 LB 1 LB 2 LB 3 Cluster RAM LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM Phase Align Buffer Deserializer Serializer TX RX Serial Signal Bank Figure 1. High-speed PSITM Block Diagram (25G01K100) with I/O Bank Structure Document #: 38-02021 Rev. *C Page 2 of 44 XCVR CNTRL & I/O I/O Bank I/O Bank LB 0 LB 7 LB 0 LB 7 LB 0 LB 7 LB 0 LB 7 2.5-Gbps Programmable Serial Interface Functional Description The 2.5-Gbps PSI is a point-to-point or point-to-multipoint programmable communications building block allowing the manipulation and transfer of data over high-speed serial links at 2.5 Gbps per serial link. The 2.5-Gbps PSI is designed to combine the high speed, predictable timing, high density, low power, and ease of use of complex programmable logic devices (CPLD) with the serializing/deserializing (SERDES) capability of high-speed serial transceivers. The architecture of the device is based on logic block clusters (LBC) and serial transceiver blocks that are connected by horizontal and vertical routing channels. Each LBC features eight individual logic blocks (LB) of 16 macrocells and two cluster memory blocks. Adjacent to each LBC is a channel memory block which is externally accessible through the I/O interface. Each transmit channel of the transceiver accepts 16 bit parallel characters, and converts it to serial data. Each receive channel accepts serial data and converts it to 16-bit parallel data, and presents these characters to the routing channels of the Programmable Logic. High-speed Transceiver The transceiver operation of the high-speed programmable serial interface devices is self-contained in a single block. It has a separate Transmit PLL (TXPLL) and a Receive Clock and Data Recovery PLL (RX CDR PLL) and a phase align buffer for flexible clocking. The transmit channel accepts a 16-bit input character from the routing channels and passes the character to the phase align buffer. This character is then serialized and output to differential CML output drivers at 2.5 Gbps. The receive channel accepts a serial bit-stream from the differential CML receiver. This bit-stream is deserialized and a 16-bit character is presented to the routing channels in the PSI device. The block also features loop-back and loop-through modes for simplified design debugging. The transceiver block interfaces to the routing channels of the PSI device through highly configurable datapath cells. For specific architecture and operation of the transceiver blocks please refer to the Serial Transceiver Operation section (page 14). The internal interfacing to the transceiver blocks of the high-speed device occur through the port definition of the high-speed transceiver block. The internal signals and their definition are described in the "Pin and Signal Description" section (page 38). These internal signals can be routed to the programmable logic by instantiation and port mapping them through hardware description using Warp Software. CY PSI + REFCLK - System Bus Programmable Host Bus Interface Optical Transceiver Optical Fiber Links IN+ Serial RD+ Data IN- RD- SD SD OUT- TD- Serial OUT+ Data TD+ Figure 2. High-speed PSI System Connections with an Optical Interface Standard Datapath Cell Figure 3 is a block diagram of the PSI datapath cell. The datapath cell contains a three-state transmit buffer, a receive buffer, and a register that can be configured as a transmit or receive register. The Transceiver Enable (TE) can be selected from one of the four global control signals(GCTL[0:3]) or from one of two Output Control Channel (OCC) signals. The transmit enable can be configured as always enabled or always disabled or it can be controlled by one of the remaining inputs to the mux. The selection is done via a mux that includes VCC and GND as inputs. One of the global clocks(GCLK[1:0], TXCLK or RXCLK) can be selected as the clock for the datapath cell register. The clock mux output is an input to a clock polarity mux that allows the transmit/receive register to be clocked on either edge of the clock. Global Routing Description The routing architecture in the PLD block of a PSI device is made up of horizontal and vertical (H&V) routing channels. These routing channels allow signals to move among I/Os, logic blocks and memories. In addition to the horizontal and vertical routing channels that interconnect the I/O banks, channel memory blocks, transceiver blocks and logic block clusters, each LBC contains a Programmable Interconnect MatrixTM (PIMTM), which is used to route signals among the logic blocks and the cluster memory blocks in the LBC. Figure 4 is a block diagram of the routing channels that interface within the PSI architecture. Document #: 38-02021 Rev. *C Page 3 of 44 2.5-Gbps Programmable Serial Interface Registered TE Mux TE Mux D From Output PIM Receive Mux 3 C RES Q C To Routing Channel Output Control Channel OCC Global Control Signals Global Clock Signals Register Receive Mux C C Transmit Mux Register Enable Mux Clock Polarity Mux C D E Q C RES Signal 3 Clock Mux 2 C C Register Reset Mux 3 C Figure 3. Block Diagram of a Standard Datapath Cell Logic Block Cluster (LBC) The PSI architecture consists of several logic block clusters, each of which have eight Logic Blocks (LBs) and two cluster memory blocks connected via a PIM, as shown in Figure 5. Each cluster memory block consists of 8-Kbit single-port RAM, which is configurable as synchronous or asynchronous. The cluster memory blocks can be cascaded with other cluster memory blocks within the same LBC as well as other LBCs to implement larger memory functions. If a cluster memory block is not specifically utilized by the designer, Cypress's Warp software can automatically use it to implement large blocks of logic. All LBCs interface with each other via horizontal and vertical routing channels. I/O Block LB LB LB LB Cluster Memory Block LB 72 LB Cluster PIM 64 LB LB Cluster Memory Block Channel Memory Block Channel memory outputs drive dedicated tracks in the horizontal and vertical routing channels 72 I/O Block 64 H-to-V PIM V-to-H PIM Pin inputs from the I/O cells drive dedicated tracks in the horizontal and vertical routing channels Figure 4. PSI Routing Interface Document #: 38-02021 Rev. *C Page 4 of 44 2.5-Gbps Programmable Serial Interface Clock Inputs G CLK [1:0], R XC LK and TX CLK 4 Logic B lock 0 CC 36 16 36 16 Logic B lock 7 CC Logic B lock 1 CC 36 16 36 16 Logic B lock 6 CC Logic B lock 2 CC 36 16 PIM 36 16 Logic B lock 5 CC Logic B lock 3 36 16 36 16 Logic B lock 4 C luster M em ory 0 25 8 25 8 C luster M em ory 1 C C = C arry C hain 64 Inputs From H orizontal R outing C hannel 64 Inputs From Vertical R outing C hannel 144 O utputs to H orizontal and V ertical cluster-to-channel P IM s Figure 5. PSI Logic Block Cluster Diagram Logic Block The LB is the basic building block of the programmable logic block of the PSI architecture. It consists of a product term array, an intelligent product-term allocator, and 16 macrocells. Product Term Array Each LB features a 72 x 83 programmable product term array. This array accepts 36 inputs from the PIM. These inputs originate from device pins and macrocell feedbacks as well as cluster memory and channel memory feedbacks. Active LOW and active HIGH versions of each of these inputs are generated to create the full 72-input field. The 83 product terms in the array can be created from any of the 72 inputs. Of the 83 product terms, 80 are for general-purpose use for the 16 macrocells in the LB. Two of the remaining three product terms in the LB are used as asynchronous set and asynchronous reset product terms. The final product term is the Product Term clock (PTCLK) and is shared by all 16 macrocells within an LB. Product Term Allocator Through the product term allocator, Warp software automatically distributes the 80 product terms as needed among the 16 macrocells in the LB. The product term allocator provides two important capabilities without affecting performance: product term steering and product term sharing. Product Term Steering Product term steering is the process of assigning product terms to macrocells as needed. For example, if one macrocell requires ten product terms while another needs just three, the product term allocator will "steer" ten product terms to one macrocell and three to the other. On PSI devices, product terms are steered on an individual basis. Any number between 1and 16 product terms can be steered to any macrocell. Product Term Sharing Product term sharing is the process of using the same product term among multiple macrocells. For example, if more than one function has one or more product terms in its equation that are common to other functions, those product terms are only created once. The PSI product term allocator allows sharing across groups of four macrocells in a variable fashion. The software automatically takes advantage of this capability so that the user does not have to intervene. Note that neither product term sharing nor product term steering have any effect on the speed of the product. All steering and sharing configurations have been incorporated in the timing specifications for the PSI devices. . Document #: 38-02021 Rev. *C Page 5 of 44 2.5-Gbps Programmable Serial Interface Macrocell Within each LB there are 16 macrocells. Each macrocell accepts a sum of up to 16 product terms from the product term array. The sum of these 16 product terms can be output in either registered or combinatorial mode. Figure 6 displays the block diagram of the macrocell. The register can be asynchronously preset or asynchronously reset at the macrocell level with the separate preset and reset product terms. Each of these product terms features programmable polarity. This allows the registers to be preset or reset based on an AND expression or an OR expression. An XOR gate in the PSI macrocell allows for many different types of equations to be realized. It can be used as a polarity mux to implement the true or complement form of an equation in the product term array or as a toggle to turn the D flip-flop into a T flip-flop. The carry-chain input mux allows additional flexibility for the implementation of different types of logic. The macrocell can utilize the carry chain logic to implement adders, subtractors, magnitude comparators, parity tree, or even generic XOR logic. The output of the macrocell is either registered or combinatorial. Carry Chain Logic The PSI macrocell features carry chain logic which is used for fast and efficient implementation of arithmetic operations. The carry logic connects macrocells in up to four LBs for a total of 64 macrocells. Effective data path operations are implemented C a rry In (fro m m a c ro c e ll n -1 ) 0 1 C through the use of carry-in arithmetic, which drives through the circuit quickly. Figure 6 shows that the carry chain logic within the macrocell consists of two product terms (CPT0 and CPT1) from the PTA and an input carry-in for carry logic. The inputs to the carry chain mux are connected directly to the product terms in the PTA. The output of the carry chain mux generates the carry-out for the next macrocell in the LB as well as the local carry input that is connected to an input of the XOR input mux. Carry-in and a configuration bit are inputs to an AND gate. This AND gate provides a method of segmenting the carry chain in any macrocell in the LB. Macrocell Clocks Clocking of the register is highly flexible. Four global synchronous clocks (GCLK[1:0], RXCLK and TXCLK) and a Product Term clock (PTCLK) are available at each macrocell register. Furthermore, a clock polarity mux within each macrocell allows the register to be clocked on the rising or the falling edge (see macrocell diagram in Figure 6). PRESET/RESET Configurations The macrocell register can be asynchronously preset and reset using the PRESET and RESET mux. Both signals are active high and can be controlled by either of two Preset/Reset product terms (PRC[1:0] in Figure 6) or GND. In situations where the PRESET and RESET are active at the same time, RESET takes priority over PRESET. PRESET M ux C a rry C h a in M ux CPT0 CPT1 C X O R In p u t M ux 3 C O u tp u t M u x 2 C PSET T o P IM FRO M P TM Up To 16 P Ts C lo c k M u x G C L K [1 :0 ], R X C L K , TXCLK P TCLK 3 C C C lo c k P o la rity M ux D Q C RES Q PRC[1:0] 0 1 C a rry O u t (to m a c ro c e ll n + 1 ) 3 C RESET M ux Figure 6. PSI Macrocell Document #: 38-02021 Rev. *C Page 6 of 44 2.5-Gbps Programmable Serial Interface Embedded Memory The 2.5-Gbps PSI family contains two types of embedded memory blocks. The channel memory block is placed at the intersection of horizontal and vertical routing channels. Each channel memory block is 4096 bits in size and can be configured as asynchronous or synchronous Dual-Port RAM, Single-Port RAM, Read-Only memory (ROM), or synchronous FIFO memory. The memory organization is configurable as 4K x 1, 2K x 2, 1K x 4 and 512 x 8. The second type of memory block is located within each LBC and is referred to as a cluster memory block. Each LBC contains two cluster memory blocks that are 8192 bits in size. Similar to the channel memory blocks, the cluster memory blocks can be configured as 8K x 1, 4K x 2, 2K x 4 and 1K x 8 and can be configured as either asynchronous or synchronous Single-Port RAM or ROM. Cluster Memory Each LB cluster of the PSI device contains two 8192-bit cluster memory blocks. Figure 7 is a block diagram of the cluster memory block and the interface of the cluster memory block to the cluster PIM. The output of the cluster memory block can be optionally registered to perform synchronous pipelining or to register asynchronous read and write operations. The output registers contain an asynchronous RESET which can be used in any type of sequential logic circuits (e.g., state machines). There are four global clocks and one local clock available for the input and the output registers. The local clock for the input registers is independent of the one used for the output registers. The local clock is generated in the user-design in a macrocell or comes from an I/O pin. Cluster Memory Initialization The cluster memory powers up in an undefined state, but is set to a user-defined known state during configuration. To facilitate the use of look-up-table (LUT) logic and ROM applications, the cluster memory blocks can be initialized with a given set of data when the device is configured at power up. For LUT and ROM applications, the user cannot write to memory blocks. Channel Memory The PSI architecture includes an embedded memory block at each crossing point of horizontal and vertical routing channels. The channel memory is a 4096-bit embedded memory block that can be configured as asynchronous or synchronous Single-Port RAM, Dual-Port RAM, ROM, or synchronous FIFO memory. Data, address, and control inputs to the channel memory are driven from horizontal and vertical routing channels. All data and FIFO logic outputs drive dedicated tracks in the horizontal and vertical routing channels. The clocks for the channel memory block are selected from four global clocks and pin inputs from the horizontal and vertical channels. The clock muxes also include a polarity mux for each clock so that the user can choose an inverted clock. Dual-Port (Channel Memory) Configuration Each port has distinct address inputs, as well as separate data and control inputs that can be accessed simultaneously. The inputs to the Dual-Port memory are driven from the horizontal and vertical routing channels. The data outputs drive dedicated tracks in the routing channels. The interface to the routing is such that Port A of the Dual-Port interfaces primarily with the horizontal routing channel and Port B interfaces primarily with the vertical routing channel. . D IN [7 :0 ] D Q C 3 W rite C o n tro l L o g ic 2 C 8 A D D R [1 2 :0 ] D Q C Row Decode (1024 Rows) WE D Q Write Pulse C 10 C lu s te r P IM R XC LK , TXC LK , G C L K [1 :0 ] Local C LK 3 C C 5 :1 3 1024x8 A s yn c h ro n o u s SRAM 8 D O U T [7 :0 ] Q C D R R ead C o n tro l L o g ic 2 C RESET R XC LK , T XCLK , G C L K [1 :0 ] Local C LK 3 C 5 :1 C Figure 7. Block Diagram of Cluster Memory Block Document #: 38-02021 Rev. *C Page 7 of 44 2.5-Gbps Programmable Serial Interface The clocks for each port of the Dual-Port configuration are selected from four global clocks and two local clocks. One local clock is sourced from the horizontal channel and the other from the vertical channel. The data outputs of the dualport memory can also be registered. Clocks for the output registers are also selected from four global clocks and two local clocks. One clock polarity mux per port allows the use of true or complement polarity for input and output clocking purposes. Arbitration The Dual-Port configuration of the Channel Memory Block provides arbitration when both ports access the same address at the same time. Depending on the memory operation being attempted, one port always gets priority. See Table 1 for details on which port gets priority for read and write operations. An active-LOW `Address Match' signal is generated when an address collision occurs. Table 1. Arbitration Result: Address Match Signal Becomes Active Port A Port Result of B Arbitration Comment Both ports read at the same time If Port B requests first then it will read the current data. The output will then change to the newly written data by Port A If Port A requests first then it will read the current data. The output will then change to the newly written data by Port B Port B is blocked until Port A is finished writing port of the FIFO can also be registered. One clock polarity mux per port allows using true or complement polarity for read and write operations. The write operation is controlled by the clock and the write enable pin. The read operation is controlled by the clock and the read enable pin. The enable pins can be sourced from horizontal or vertical channels. Channel Memory Initialization The channel memory powers up in an undefined state, but is set to a user-defined known state during configuration. To facilitate the use LUT logic and ROM applications, the channel memory blocks can be initialized with a given set of data when the device is configured at power up. For LUT and ROM applications, the user cannot write to memory blocks. Channel Memory Routing Interface Similar to LBC outputs, the channel memory blocks feature dedicated tracks in the horizontal and vertical routing channels for the data outputs and the flag outputs, as shown in Figure 8. This allows the channel memory blocks to be expanded easily. These dedicated lines can be routed to I/O pins as chip outputs or to other LB clusters to be used in logic equations. All channel memory inputs are driven from the routing channels Read Read No arbitration required Write Read Port A gets priority 4096-bit Dual Port Array Configurable as Async/Sync Dual Port or Sync FIFO Configurable as 4Kx1, 2Kx2, 1Kx4 and 512x8 block sizes Global Clock Signals Read Write Port B gets priority GCLK[3:0] Vertical Channel Write Write Port A gets priority All channel memory outputs drive dedicated tracks in the routing channels Horizontal Channel FIFO (Channel Memory) Configuration The channel memory blocks are also configurable as synchronous FIFO RAM. In the FIFO mode of operation, the channel memory block supports all normal FIFO operations without the use of any general-purpose logic resources in the device. The FIFO block contains all of the necessary FIFO flag logic, including the read and write address pointers. The FIFO flags include an empty/full flag (EF), half-full flag (HF), and programmable almost-empty/full (PAEF) flag output. The FIFO configuration has the ability to perform simultaneous read and write operations using two separate clocks. These clocks may be tied together for a single operation or may run independently for asynchronous read/write (with reference to . each other) applications. The data and control inputs to the FIFO block are driven from the horizontal or vertical routing channels. The data and flag outputs are driven onto dedicated routing tracks in both the horizontal and vertical routing channels. This allows the FIFO blocks to be expanded by using multiple FIFO blocks on the same horizontal or vertical routing channel without any speed penalty. In FIFO mode, the write and read ports are controlled by separate clock and enable signals. The clocks for each port are selected from four global clocks and two local clocks. One local clock is sourced from the horizontal channel and the other from the vertical channel. The data outputs from the read Document #: 38-02021 Rev. *C Figure 8. Block Diagram of Channel Memory Block I/O Banks The PSI interfaces the horizontal and vertical routing channels to the pins through I/O banks. There are several I/O banks per device as shown in Figure 9 and all I/Os from an I/O bank are located in the same section of a package for PCB layout convenience. There exist two kinds of I/O banks; fixed-signal I/O banks and user programmable I/O banks. The first fixed signal bank is the Serial Signal Bank. This bank includes all differential serial data transmission and receive signals. The second bank is the Transceiver Control Bank. This bank includes all static signal pins required for the configuration and operation of the transceiver blocks in each of the PSI devices. Each PSI device has several types of user programmable I/O banks. The table in the next column (PSI programmable I/O Banks) indicates the availability of each type of programmable bank. Supported I/O standards for each bank are addressed by the appropriate VREF and VCCIO voltages. All the VREF and VCCIO pins in an I/O bank must be connected to the same VREF and VCCIO voltage respectively. This requirement restricts the number of I/O standards supported by an I/O bank at any given Page 8 of 44 2.5-Gbps Programmable Serial Interface time. It also dictates the I/O standard used for the GCTL[3:0] pins. The architecture defining each programmable I/O bank consists of several I/O cells, where each I/O cell contains an input/output register, an output enable register, programmable slew rate control and programmable bus hold control logic. Each I/O cell drives a pin output of the device; the cell also supplies an input to the device that connects to a dedicated track in the associated routing channel. There are four dedicated inputs (GCTL[3:0]) that are used as Global Control Signals available to every I/O cell. These global control signals may be used as output enables, register resets and register clock enables as shown in Figure 10. Each global control originates from a particular bank though they can be used to control any I/O cell in the device. The input signalling standard for a particular global control signal is same as the I/O standard for bank from which it originates. Table 2. IO Standards I/O Standard LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V PCI GTL+ SSTL3 I SSTL3 II SSTL2 I SSTL2 II HSTL I HSTL II HSTL III HSTL IV 0.9 1.3 1.3 1.15 1.15 0.68 0.68 0.68 0.68 1.1 1.7 1.7 1.35 1.35 0.9 0.9 0.9 0.9 VREF (V) Min N/A Max 3.3 V 3.3 V 3.0 V 2.5 V 1.8 V 3.3 V N/A 3.3 V 3.3 V 2.5 V 2.5 V 1.5 V 1.5 V 1.5 V 1.5 V N/A N/A N/A N/A N/A N/A 1.5 1.5 1.5 1.25 1.25 0.75 0.75 1.5 1.5 VCCIO Termination Voltage (VTT) I/O Bank I/O Bank I/O Bank I/O Bank I/O Bank Serial Bank XCVR CNTL & I/O PSI I/O Banks for Global Controls GCTL[0] Bank 0 GCTL[1] 5 GCTL[2] 6 GCTL[3] 7 I/O Bank I/O Bank I/O Bank Figure 9. PSI I/O Bank Block Diagram PSI Programmable I/O Banks Device Flexible SemiFlexible Specific VCCIO VREF I/O Banks for Global CLKs GCLK[0] Bank 0 GCLK[1] 5 25G01K100 Bank[0:3, 5] Bank[4] Bank[6:7] VCCIO=3.3V 1.5V 0.68-0.90V Document #: 38-02021 Rev. *C Page 9 of 44 2.5-Gbps Programmable Serial Interface Registered OE Mux OE Mux D From Output PIM Input Mux 3 C RES Q C To Routing Channel Output Control Channel OCC Global Control Signals Global Clock Signals Register Input Mux C C Output Mux Register Enable Mux Clock Polarity Mux C D E Q C RES Bus Hold I/O C 3 Clock Mux Slew Rate Control C 2 C C Register Reset Mux 3 C Figure 10. Block Diagram of I/O Cell I/O Cell Figure 10 is a block diagram of the PSI I/O cell. The I/O cell contains a three-state input buffer, an output buffer, and a register that can be configured as an input or output register. The output buffer has a slew rate control option that can be used to configure the output for a slower slew rate. The input of the device and the pin output can each be configured as registered or combinatorial, however only one path can be configured as registered in a given design. The output enable can be selected from one of the four global control signals or from one of two OCC signals. The output enable can be configured as always enabled or always disabled or it can be controlled by one of the remaining inputs to the mux. The selection is done via a mux that includes VCC and GND as inputs. One of the global clocks can be selected as the clock for the I/O cell register. The clock mux output is an input to a clock polarity mux that allows the input/output register to be clocked on either edge of the clock. Slew Rate Control The output buffer has a slew rate control option. This allows the ouput buffer to slew at a fast rate (3 V/ns) or a slow rate (1 V/ns). All I/Os default to fast slew rate. For designs concerned with meeting FCC emissions standards the slow edge provides for lower system noise. For designs requiring very high performance the fast edge rate provides maximum system performance. Programmable Bus Hold On each I/O pin, user-programmable bus-hold is included. Bus-hold, which is an improved version of the popular internal Device 25G01K100 pull-up resistor, is a weak latch connected to the pin that does not degrade the device's performance. As a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in businterface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. For more information, see the application note "Understanding Bus-Hold - A Feature of Cypress CPLDs." Clocks PSI has four primary internal global clock trees in the CPLD portion of the device (INTCLK[3:0]). Each of these clock trees distributes a clock signal to every cluster, channel memory, and I/O cell in the CPLD. The global clock trees are designed such that the clock skew is minimized while maintaining an acceptable clock delay. Each of the internal global clocks can choose from two input sources for the clock signal: a PLL derived output or another one as shown in the table below. ININTCLK[0] TCLK[1] GCLK[0] GCLK[1] INTCLK[2] TXCLK INTCLK[3] RXCLK GCLK[0] and GCLK[1] are accessible through pins on the device package. TXCLK and RXCLK are provided internally to the device. TXCLK (transmit clock) is intended for data transfer from the CPLD block to the transmit channel of the transceiver block. RXCLK (receive clock) is intended for data transfer from the receive channel of the transceiver block to the CPLD block. The TXCLK and RXCLK can also be used for logic inside the CPLD block, e.g., for data processing. Document #: 38-02021 Rev. *C Page 10 of 44 2.5-Gbps Programmable Serial Interface Clock Tree Distribution The global clock tree performs two primary functions. First, the clock tree generates the four internal global clocks by multiplexing four reference clocks derived from the Transceiver Blocks and from the package pins and four PLL driven clocks. Second, the clock tree distributes the four global clocks to every cluster, channel memory, I/O block, and datapath cell on the die. The global clock tree is designed such that the clock skew is minimized while maintaining an acceptable clock delay. Spread AwareTM PLL The 2.5-Gbps PSI device features an on-chip PLL designed using Spread AwareTM technology for low EMI applications. In general, PLLs are used to implement time-division-multiplex circuits to achieve higher performance with fewer device resources. For example, a system that operates on a 32-bit data path that runs at 40 MHz can be implemented with 16-bit circuitry that runs internally at 80 MHz. PLLs can also be used to take advantage of the positioning of the internally generated clock edges to shift performance towards improved setup, hold or clock-to-out times. There are several frequency multiply (X1, X2, X3, X4, X5, X6, X8, X16) and divide (/1, /2, /3, /4, /5, /6, /8, /16) options available to create a wide range of clock frequencies from a single clock input (GCLK[0]). For increased flexibility, there are seven phase shifting options which allow clock skew/de-skew by 45, 90, 135, 180, 225, 270, or 315. The Spread Aware feature refers to the ability of the PLL to track a spread-spectrum input clock such that its spread is seen on the output clock with the PLL staying locked. The total o f f - c h ip s i g n a l ( e x t e r n a l f e e d b a c k ) IN T C L K 0 , IN T C L K 1 , IN T C L K 2 , IN T C L K 3 A n y R e g is t e r amount of spread on the input clock should be limited to 0.6% of the fundamental frequency. Spread Aware feature is supported only with X1, X2 and X4 multiply options. The Voltage Controlled Oscillator (VCO), the core of the PSI PLL is designed to operate within the frequency range of 100 MHz to 266 MHz. Hence, the multiply option combined with input (GCLK[0]) frequency should be selected such that this VCO operating frequency requirement is met. This is demonstrated in Table 3 (columns 1, 2, and 3). Another feature of this PLL is the ability to drive the output clock (INTCLK) off the PSI chip to clock other devices on the board, as shown in Figure 11 below. This off-chip clock is half the frequency of the output clock as it has to go through a register (I/O register or a macrocell register). This PLL can also be used for board deskewing purpose by driving a PLL output clock off-chip, routing it to the other devices on the board and feeding it back to the PLL's external feedback input (GCLK[1]). When this feature is used, only limited multiply, divide and phase shift options can be used. Table 3 describes the valid multiply and divide options that can be used without an external feedback. Table 4 describes the valid multiply and divide options that can be used with an external feedback. Table 5 describes the valid phase shift options that can be used with or without an external feedback. Table 6 is an example of the effect of all the available divide and phase shift options on a VCO output of 250 MHz. It also shows the effect of division on the duty cycle of the resultant clock. Note that the duty cycle is 50-50 when a VCO output is divided by an even number. Also note that the phase shift applies to VCO output and not to the divided output. S e n d a g lo b a l c lo c k o f f c h i p G CLK1 N o r m a l I / O s ig n a l p a t h L o c k D e t e c t / I O p in C lo c k T r e e D e la y 2 C P h a s e s e le c t io n C D iv id e 1 - 6 ,8 ,1 6 IN T C L K 0 G C LK 0 / fb fb Lock P h a s e s e le c t io n 2 C / C lk 0 0 C lk 4 5 0 C lk 9 0 0 D iv id e 1 -6 ,8 ,1 6 IN T C L K 1 G CLK1 G CLK0 S o u rc e C lo c k P h a s e s e le c t io n 2 C C lk 1 3 5 0 C lk 1 8 0 0 C lk 2 2 5 0 C lk 2 7 0 0 / D iv id e 1 - 6 ,8 ,1 6 IN T C L K 2 TXCLK 2 PLL C lk 3 1 5 0 X 1, X 2, X 3, X 4, X 5, X6, X8, X16 P h a s e s e le c t io n C D iv id e 1 -6 ,8 ,1 6 IN T C L K 3 RXCLK 2 / GCLK[1:0] C Figure 11. Block Diagram of Spread Aware PLL for CYP25G01K100 Document #: 38-02021 Rev. *C Page 11 of 44 2.5-Gbps Programmable Serial Interface Table 3. PLL Multiply and Divide Options--without INTCLK1 Feedback Input Frequency (GCLK[0]) fPLLI (MHz) DC-12.5 100-133 50-133 33.3-88.7 25-66 20-53.2 16.6-44.3 12.5-33 12.5-16.625 Valid Multiply Options Value N/A 1 2 3 4 5 6 8 16 VCO Output Frequency (MHz) N/A 100-133 100-266 100-266 100-266 100-266 100-266 100-266 200-266 Value N/A 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 Valid Divide Options Output Frequency (INTCLK[3:0]) fPLLO (MHz) DC-12.5 6.25-133 6.25-266 6.25-266 6.25-266 6.25-266 6.25-266 6.25-266 6.25-266 Off-chip Clock Frequency DC-6.25 3.125-66 3.125-133 3.1-266 3.125-133 3.1-133 3.1-133 3.125-133 3.125-133 Table 4. PLL Multiply and Divide Options--with External Feedback Valid Multiply Options Input (GCLK) Frequency fPLLI (MHz) 50-133 25-66.5 16.67-44.33 12.5-33.25 12.5-26.6 12.5-22.17 12.5-16.63 Value 1 1 1 1 1 1 1 VCO Output Frequency (MHz) 100-266 100-266 100-266 100-266 125-266 150-266 200-266 Value 1 2 3 4 5 6 8 Valid Divide Options Output (INTCLK) Frequency fPLLO (MHz) 100-266 50-133 33.33-88.66 25-66.5 25-53.2 25-44.34 25-33.25 Off-chip Clock Frequency 50-133 25-66.5 16.67-44.33 12.5-33.25 12.5-26.6 12.5-22.17 12.5-16.63 Table 5. PLL Phase Shift Options with and without INTCLK1 Feedback Without External Feedback 0,45, 90, 135, 180, 225, 270, 315 Table 6. Timing of Clock Phases for all Divide Options for a VCO Output Frequency of 250 MHz Divide Factor 1 2 3 4 5 6 8 16 Timing Model One important feature of the 2.5-Gbps PSI is the simplicity of its timing. All combinatorial and registered/synchronous delays are worst case and system performance is static (as shown in the AC specs section) as long as data is routed through the same horizontal and vertical channels. Figure 12 illustrates the true timing model for the programmable LB of the device. For synchronous clocking of macrocells, a delay is incurred from macrocell clock to macrocell clock of separate Period (ns) 4 8 12 16 20 24 32 64 Duty Cycle% 40-60 50 33-67 50 40-60 50 50 50 0 (ns) 0 0 0 0 0 0 0 0 45 (ns) 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 90 (ns) 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 135 (ns) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 180 (ns) 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 225 (ns) 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 270 (ns) 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 315 (ns) 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 With External Feedback 0 LBs within the same cluster, as well as separate LBs within different clusters. This is shown as tSCS and tSCS2 in Figure 12. For combinatorial paths, any input to any output (from corner to corner on the device), incurs a worst-case delay in the 100K gate PSI regardless of the amount of logic or which horizontal and vertical channels are used. This is the tPD shown in Figure 12. For synchronous systems, the input set-up time to the output macrocell register and the clock to output time are shown as the parameters tMCS and tMCCO shown in the Document #: 38-02021 Rev. *C Page 12 of 44 2.5-Gbps Programmable Serial Interface Figure 12. These measurements are for any output and synchronous clock, regardless of the logic placement. PSI features: * no dedicated vs. I/O pin delays * no penalty for using 0-16 product terms * no added delay for steering product terms * no added delay for sharing product terms * no output bypass delays. The simple timing model of the 2.5-Gbps PSI eliminates unexpected performance penalties. tSCS GCLK[1:0], RXCLK, TXCLK 4 4 4 4 LB 0 LB 1 LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 2 PIM LB 5 LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 8 Kb SRAM RAM tMCS LB 3 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM LB 4 8 Kb SRAM GCLK[1:0], RXCLK, TXCLK 4 4 4 4 tSCS2 LB 0 LB 1 LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 2 PIM LB 5 LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM RAM tPD LB 3 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM GCLK[1:0], TXCLK, RXCLK 4 4 4 4 LB 0 LB 1 LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 0 LB 1 RAM LB 7 LB 6 Channel LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM RAM LB 4 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM LB 4 Cluster RAM tMCCO Figure 12. Timing Model for 100K gate PSI Devices Document #: 38-02021 Rev. *C Page 13 of 44 2.5-Gbps Programmable Serial Interface Serial Transceiver Operation The PSI transceiver block is a highly configurable transceiver designed to support reliable transfer of large quantities of data, using high-speed serial links, from one or multiple sources to one or multiple destinations. This block supports serialization of a 16-bit dataword in the transmit side, and clock recovery and deserialization on the receive side. The interconnection between the serial transceiver block and the embedded programmable logic has to be specified using hardware description in Warp Software. the bit-rate clock generated by the Transmit PLL clock multiplier. TXD[15] is the most significant bit of the output word, and is transmitted first on the serial interface. Serial Output Driver The serial interface Output Driver makes use of high-performance differential CML (Current Mode Logic) to provide a source-matched driver for the transmission lines. This driver receives its data from the Transmit Shifters or the receive loopback data. The outputs have signal swings equivalent to that of standard LVPECL drivers, and are capable of driving AC-coupled optical modules or transmission lines. Receive Data Path Serial Line Receivers A differential line receiver, IN, is available for accepting the input serial data stream. The serial line receiver inputs can accommodate high wire interconnect and filtering losses or transmission line attenuation (VSE > 25 mV, or 50 mV peak-topeak differential), and can be AC-coupled to +3.3V or +5V powered fiber-optic interface modules. The common-mode tolerance of these line receivers accommodates a wide range of signal termination voltages. Lock to Data Control Line Receiver routed to the clock and data recovery PLL is monitored for * status of signal detect (SD) pin * status of LOCKREF pin * received data stream outside normal frequency range (100 ppm). This status is presented on the LFI (Line Fault Indicator) output signal, which changes asynchronously in the cases when SD or LOCKREF goes from HIGH to LOW. Otherwise, it changes synchronously to the REFCLK. Clock/Data Recovery The extraction of a bit-rate clock and recovery of data bits from received serial stream is performed by a Clock/Data Recovery (CDR) block. The clock extraction function is performed by high-performance embedded PLL that tracks the frequency of the incoming bit stream and aligns the phase of the internal bitrate clock to the transitions in the selected serial data stream. CDR accepts a character-rate (bit-rate / 16) reference clock on the REFCLK input. This REFCLK input is used to ensure that the VCO (within the CDR) is operating at the correct frequency (rather than some harmonic of the bit-rate), to improve PLL acquisition time, and to limit unlocked frequency excursions of the CDR VCO when no data is present at the serial inputs. Regardless of the type of signal present, the CDR will attempt to recover a data stream from it. If the frequency of the recovered data stream is outside the limits set by the range controls, the CDR PLL will track REFCLK instead of the data stream. When the frequency of the selected data stream returns to a valid frequency, the CDR PLL is allowed to track the received data stream. The frequency of REFCLK is required to be within 100 ppm of the frequency of the clock that drives the REFCLK signal of the remote transmitter to ensure a lock to the incoming data stream. High-speed PSI Transceiver Operation Registering TXD[15:0] Data Before it enters Serial Transceiver Block Before the 16-bit parallel input data TXD[15:0] enters the serial transceiver block, it is required to register this data in a standard data path cell without any output enables. It is also required that these datapath cells are clocked on the rising edge of the global TXCLK. Transmit Data Path The registered 16-bit parallel TXD input data from the programmable LB of the device is input into the input register of the serial transceiver block. This input register is clocked using TXCLK, which is one of the four global clocks of the programmable logic. Phase-Align Buffer Data from the input register is passed to a phase-align buffer (FIFO). This buffer is used to absorb clock phase differences between the transmit input clock entering the serial transceiver and the internal character clock. Initialization of the phase-align buffer takes place when the FIFO_RST signal is asserted LOW. When FIFO_RST is returned HIGH, the present input clock phase relative to TXCLK is set. Once set, the input clock is allowed to skew in time up to half a character period in either direction relative to REFCLK (i.e., 180). This time shift allows the delay path of the character clock (relative to REFCLK) to change due to operating voltage and temperature while not effecting the desired operation. FIFO_RST is an asynchronous signal. FIFO_ERR is the transmit FIFO Error indicator. When HIGH, the transmit FIFO has either under or overflowed. The FIFO can be externally reset or logically reset by PSI logic to clear the error indication or if no action is taken, the internal clearing mechanism will clear the FIFO in nine clock cycles. When the FIFO is being reset, the output data is 1010. Transmit PLL Clock Multiplier The Transmit PLL Clock Multiplier accepts an external clock at the REFCLK input, and multiplies that clock by 16 to generate a bit-rate clock (2.5 Gbps) for use by the transmit shifter. The operating serial signaling rate and allowable range of REFCLK frequencies are listed in the High-speed PSI Transceiver Timing Parameter Values table under "REFCLK Timing Parameters" (see page 24). The REFCLK input is a standard LVPECL input. Serializer The parallel data from the phase-align buffer is passed to the Serializer which converts the parallel data to serial data using Document #: 38-02021 Rev. *C Page 14 of 44 2.5-Gbps Programmable Serial Interface External Filter The CDR circuit uses external capacitors for the PLL filter. A 0.1-F capacitor needs be connected between RXCN1 and RXCP1. Similarly a 0.1-F capacitor needs to be connected between RXCN2 and RXCP2. The recommended packages and dielectric material for these capacitors are 0805 X7R or 0603 X7R. These capacitors should be surface mount packages and be placed as close as possible to the device. Deserializer The CDR circuit extracts bits from the serial data stream and clocks these bits into the Deserializer at the bit-clock rate. The Deserializer converts serial data into parallel data. RXD[15] is the most significant bit of the output word and is received first on the serial interface. This RXD[15:0] data is output registered and fed to the programmable LB of the device. Registering RXD[15:0] Data Before It Enters Programmable LB Before the RXD[15:0] enters the programmable LB it is required to register these signals in standard datapath cells without any output enables. It is also required to clock these standard datapath cells using the rising edge of the global RXCLK. Loopback/Timing Modes High-speed PSI supports various loopback modes as described below. Facility Loopback (Line Loopback With Retiming) When the LINELOOP signal is set HIGH, the Facility Loopback mode is activated and the high-speed serial receive data (IN) is presented to the high-speed transmit output (OUT) after retiming. In Facility Loopback mode, the high-speed receive data (IN) is also converted to parallel data and presented to the low-speed receive data output pins (RXD[15:0]). The receive recovered clock is also divided down and presented to the low speed clock output (RXCLK). Equipment Loopback (Diagnostic Loopback With Retiming) When the DIAGLOOP signal is set HIGH, transmit data is looped back to the RX PLL, replacing IN. Data is looped back from the parallel TX inputs to the parallel RX outputs. The data is looped back at the internal serial interface and goes through transmit shifter and the receive CDR. SD is ignored in this mode. Line Loopback Mode (Non-retimed Data) When the LOOPA signal is set HIGH, the RX serial data is directly buffered out to the transmit serial data. The data at the serial output is not retimed. Loop Timing Mode When the LOOPTIME signal is set HIGH, the TX PLL is bypassed and receive bit-rate clock is used for transmit side shifter. Reset Modes for the serial transceiver All logic circuits in the serial transceiver block can be reset using RESET and FIFO_RST signals. When RESET is set LOW, all logic circuits in the serial transceiver except FIFO are internally reset. When FIFO_RST is set LOW, the FIFO logic is reset. Power-down Mode for serial transceiver High-speed PSI transceiver block provide a power-down signal PWRDN. When LOW, this signal powers down the entire serial transceiver block to a minimal power dissipation state. RESET and FIFO_RST signals should be asserted LOW along with PWRDN signal to ensure low-power dissipation. Document #: 38-02021 Rev. *C Page 15 of 44 2.5-Gbps Programmable Serial Interface REFCLK+ TXCLK FIFO_RST TXD[0:15] FIFO_ERR TXCLK 16 Input Register /16 TX PLL X16 FIFO /16 Recovered Bit-Clock RX CDR PLL Lock-to-Ref LOOPTIME DIAGLOOP Shifter Output Register RXCLK RXD[0:15] 16 Shifter LINELOOP LOOPA Lock-to-Data/ Clock Control Logic PWRDN LOCKREF OUT+ SD LFI RESET IN+ Figure 13. High-speed PSI Transceiver Logic Block Diagram[2] Note: 2. All signal names outside the dotted box have dedicated pins in the package. Other signals are internal and must be port-mapped to programmable logic using hardware description in Warp software. Document #: 38-02021 Rev. *C Retimed Data Page 16 of 44 2.5-Gbps Programmable Serial Interface IEEE 1149.1-compliant JTAG Operation The 2.5-Gbps PSI has an IEEE standard 1149.1 JTAG interface for both Boundary Scan and ISR operations. Four dedicated pins are reserved on each device for use by the Test Access Port (TAP). The serial transceiver block of this device does not support JTAG since most of the blocks in the serial transceiver block are analog. Hence the serial transceiver portion is not a part of the JTAG test chain. Boundary Scan The 2.5-Gbps PSI supports Bypass, Sample/Preload, Extest, Intest, Idcode and Usercode boundary scan instructions. The JTAG interface is shown in Figure 14. Instruction Register TDI TDO There are multiple configuration options available for issuing the IEEE std 1149.1 JTAG instructions to the PSI. The first method is to use a PC with the C3 ISR programming cable and software. With this method, the ISR pins of the PSI devices in the system are routed to a connector at the edge of the printed circuit board. The C3 ISR programming cable is then connected between the PC and this connector. A simple configuration file instructs the ISR software of the programming operations to be performed on the PSI devices in the system. The ISR software then automatically completes all of the necessary data manipulations required to accomplish configuration, reading, verifying, and other ISR functions. For systems with embedded controllers/processors, a controller/processor may be used to configure the PSI. The PSI ISR software assists in this method by converting the device HEX file into the ISR serial stream that contains the ISR instruction information and the addresses and data of locations to be configured. The controller/processor then simply directs this ISR stream to the chain of PSI devices to complete the desired reconfiguration or diagnostic operations. Contact your local sales office for information on availability of this option. Programming The on-chip EEPROM device of the CPLD block is programmed by issuing the appropriate IEEE std 1149.1 JTAG instruction. This can be done automatically using ISR/STAPL software. The configuration bits are sent from a PC through the JTAG port into the PSI via the C3 ISR programming cable. The data is then passed to the internal EEPROM through the Non-Volatile (NV) port of the CPLD block. For more information on how to program the PSI through ISR/STAPL, please refer to the ISR/STAPL User Guide. Third-Party Programmers Cypress support is available on a wide variety of third-party programmers. All major programmers (including BP Micro, System General, Hi-Lo) support the PSI family. TMS TCLK JTAG TAP CONTROLLER Bypass Reg. Boundary Scan idcode Usercode ISR Prog. Data Registers Figure 14. JTAG Interface In-System ReprogrammingTM (ISRTM) In-System Reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. This combination means design changes during debug or field upgrades do not cause board respins. The 2.5-Gbps PSI implements ISR by providing a JTAG compliant interface for on-board programming, robust routing resources for pinout flexibility, and a simple timing model for consistent system performance. Configuration The CPLD block in the 2.5-Gbps PSI is designed with SelfBoot capability. An embedded on-chip EEPROM is used to store configuration data. For PSI devices, programming is defined as the loading of a user's design into the internal EEPROM. Configuration, on the other hand, is defined as the loading of a user's design into the volatile CPLD block. Configuration can begin in two ways. It can be initiated by toggling the Reconfig pin from LOW to HIGH, or by issuing the appropriate IEEE std 1149.1 JTAG instruction to the PSI device via the JTAG interface. There are two IEEE std 1149.1 JTAG instructions that initiate configuration of the PSI. The Self Config instruction causes the PSI to (re)configure with data store in the internal EEPROM. The Load Config instruction causes the PSI to (re)configure with data provided by other sources such as a PC, Automatic Test Equipment (ATE), or an embedded micro-controller/processor via the JTAG port. Development Software Support Warp Warp is a state-of-the-art design environment for designing with Cypress programmable logic. Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware Description Language (HDL) for design entry. Warp accepts VHDL or Verilog input, synthesizes and optimizes the entered design, and outputs a configuration bitstream for the desired PSI device. For simulation, Warp provides a graphical waveform simulator as well as VHDL and Verilog Timing Models. VHDL and Verilog are open, powerful, non-proprietary Hardware Description Languages (HDLs) that are standards for behavioral design entry and simulation. HDL allows designers to learn a single language that is useful for all facets of the design process. Third-party Software Cypress products are supported in a number of third-party design entry and simulation tools. Refer to the third-party software data sheet or contact your local sales office for a list of currently supported third party vendors. Document #: 38-02021 Rev. *C Page 17 of 44 2.5-Gbps Programmable Serial Interface Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Soldering Temperature................................................. 220C Ambient Temperature with Power Applied............................................... -40C to +85C Junction Temperature .................................................. 135C VCC relative to Ground Potential...................... -0.5V to 4.2V VCCIO relative to Ground Potential................... -0.5V to 4.6V DC Voltage Applied to Outputs in High-Z State -0.5V to 4.5V Range Commercial Output Current into LVCMOS Outputs (LOW)............. 30 mA DC Input voltage......................... ......................-0.5V to 4.5V DC Current into Outputs...................... ................... 20 mA[3] Static Discharge Voltage........................................... > 1100V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Ambient Temperature 0C to +70C VCC VDDQ 3.3V 10% 1.4V to 1.6V Operating Range Range Commercial Ambient Temperature 0C to +70C Junction Temperature 0C to +85C Output Condition 3.3V 2.5V 1.8V 1.5V VCCIO 3.3V 0.3V 2.5V 0.2V 1.8V 0.15V 1.5V 0.1V VCC 3.3V 0.3V VCCJTAG/ VCCCNFG Same as VCCIO VCCPLL Same as VCC VCEP 3.3V 0.3V Test Waveforms to High-speed PSI Transceiver Block 3.0V Vth=1.4V GND < 1 ns 2.0V 0.8V 3.0V 2.0V 0.8V Vth=1.4V < 1 ns 80% 20% 150 ps VICLL VICHH 80% 20% 150 ps (a) LVTTL Input Test Waveform VIEHH 80% 20% 1 ns VIELL 80% 20% 1 ns (b) CML Input Test Waveform (c) LVPECL Input Test Waveform AC Test Loads to High-speed Transceiver Block 3.3V OUTPUT R1 = 330 R2 = 510 CL 10 pF (Includes fixture and probe capacitance) CL R2 R1 OUT+ OUT- RL RL = 100 (a) TTL AC Test Load Note: 3. DC current into outputs is 36 mA with HSTL III and 48 mA with HSTL IV. (b) CML AC Test Load Document #: 38-02021 Rev. *C Page 18 of 44 2.5-Gbps Programmable Serial Interface Electrical Characteristics Over the Operating Range DC Characteristics VCCIO = 3.3V VCCIO = 2.5V VCCIO = 1.8V Parameter Description VDRINT VDRIO IIX IOZ IOS[4] IBHL IBHH IBHLO IBHHO Capacitance Parameter CI/O CPCI CCLK CINPECL CSD1 CINC1 Description Input/Output Capacitance PCI compliant I/O Capacitance Clock Signal Capacitance PECL Input Capacitance SD Pin Input Capacitance CML Input Capacitance Test Conditions Vin = VCCIO @ f = 1 MHz 25C Vin = VCCIO @ f = 1 MHz 25C Vin = VCCIO @ f = 1 MHz 25C VCC = 3.3V @ f = 1 MHz 25C VCC = 3.3V @ f = 1 MHz 25C VCC = 3.3V @ f = 1 MHz 25C 5 Min. Max. 10 8 12 4 5 4 Unit pF pF pF pF pF pF Data Retention VCC Voltage (config data may be lost below this) Data Retention VCCIO Voltage (config data may be lost below this) Input Leakage Current Output Leakage Current Output Short Circuit Current GND VI 3.6V GND VO VCCIO VCCIO = Max., VOUT = 0.5V +40 -40 +250 -250 Test Conditions Min. Max. Min. Max. Min. Max. Unit 1.5 1.2 -10 -10 10 10 -160 +30 -30 +200 -200 1.5 1.2 -10 -10 10 10 -160 +25 -25 1.5 1.2 -10 -10 10 10 V V A A A A +150 A -150 A -160 mA Input Bus Hold LOW Sustaining Current VCC = Min., VPIN = VIL Input Bus Hold HIGH Sustaining Current VCC = Min., VPIN = VIH Input Bus Hold LOW Overdrive Current VCC = Max. Input Bus Hold HIGH Overdrive Current VCC = Max. DC Characteristics (I/O) Input/Output Standard LVTTL -2 mA LVTTL -4 mA LVTTL -6 mA LVTTL -8 mA LVTTL -12 mA LVTTL -16 mA LVTTL -24 mA LVCMOS LVCMOS3 LVCMOS2 1.8 3.3 VREF (V) N/A VCCIO (V) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.0 2.5 VOH (V) @ IOH = -2 mA -4 mA -6 mA -8 mA -12 mA -16 mA -24 mA -0.1 mA -0.1 mA -0.1 mA -1.0 mA -2.0 mA LVCMOS18 3.3V PCI - 2 mA -0.5 mA VOH (Min.) 2.4 2.4 2.4 2.4 2.4 2.4 2.4 VCCIO - 0.2V VCCIO - 0.2V 2.1 2.0 1.7 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 0.1 mA 0.1 mA 0.1 mA 1.0 mA 2.0 mA VOL (V) @ IOL = VOL (Max.) 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.2 0.2 0.2 0.4 0.7 0.45 0.1VCCIO 0.65VC VCCIO+0.3 CIO VIH (V) Min. Max. VIL (V) Min. Max. 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.7V 2.0 V VCCIO + 0.3 -0.3V 2.0 V VCCIO + 0.3 -0.3V 2.0 V VCCIO + 0.3 -0.3V 2.0 V VCCIO + 0.3 -0.3V 2.0 V VCCIO + 0.3 -0.3V 2.0 V VCCIO + 0.3 -0.3V 2.0 V VCCIO + 0.3 -0.3V 2.0V VCCIO + 0.3 -0.3V 2.0V 1.7V VCCIO + 0.3 -0.3V VCCIO + 0.3 -0.3V VCCIO-0.45V 2.0 mA 0.9VCCIO 1.5 mA -0.3V 0.35V CCIO 0.5VCC VCCIO+0.5 -0.5V 0.3VC IO CIO Note: 4. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT=0.5V has been chosen to avoid test problems caused by tester ground degradation. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-02021 Rev. *C Page 19 of 44 2.5-Gbps Programmable Serial Interface DC Characteristics (I/O) Input/Output Standard GTL+ SSTL3 I SSTL3 II SSTL2 I SSTL2 II HSTL I HSTL II HSTL III HSTL IV VREF (V) 0.9 1.3 1.3 1.1 1.7 1.7 VCCIO (V) Note 5 3.3 3.3 2.5 2.5 1.5 1.5 1.5 1.5 -8 mA -16 mA VCCIO-1.1V VCCIO-0.9V VOH (V) @ IOH = VOH (Min.) VOL (V) @ IOL = 36 mA[6] 8 mA 16 mA VOL (Max.) 0.6 0.7 0.5 0.54 0.35 0.4 0.4 0.4 0.4 Min. VREF+ 0.2 VREF+ VCCIO+0.3 0.2 VREF+ VCCIO+0.3 0.2 VREF+ VCCIO+0.3 0.18 VREF+ VCCIO+0.3 0.18 VREF+ VCCIO+0.3 0.1 VREF+ VCCIO+0.3 0.1 VREF+ VCCIO+0.3 0.1 VREF+ VCCIO+0.3 0.1 Min. 2.0 -0.3 VIH (V) Max. VIL (V) Min. Max. VREF- 0.2 -0.3V VREF- 0.2 -0.3V VREF- 0.2 -0.3V VREF- 0.18 -0.3V VREF- 0.18 -0.3V VREF- 0.1 -0.3V VREF- 0.1 -0.3V VREF- 0.1 -0.3V VREF- 0.1 Max. VCC - 0.3 0.8 50 -50 200 400 VCC - 1.2 VIN = VIEHH Max. VIN = VIELL Min. 100 differential load 100 differential load 600 1200 VCC - 0.3 Unit V V A A mV mV V V A A V V A mV % mA mV mV 1.15 1.35 1.15 1.35 0.68 0.68 0.68 0.68 0.9 0.9 0.9 0.9 -7.6 mA VCCIO-0.62V 7.6 mA -15.2 mA VCCIO-0.43V 15.2 mA -8 mA -16 mA -8 mA -8 mA VCCIO-0.4V VCCIO-0.4V VCCIO-0.4V VCCIO-0.4V 8 mA 16 mA 24 mA 48 mA Parameter SD Pin LVTTL Inputs VIHT VILT IIHT IILT VINSGLE VDIFFE VIEHH VIELL IIEH IIEL VOHC VOLC IACCM VACCM ZD ZSE ZMSE IDSHORT VDIFFOC VSGLOC Description Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Input Single-ended Swing Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage (VCC Referenced) Output LOW Voltage (VCC Referenced) AC Common Mode Current AC Common Mode Voltage Differential Output Impedance Single Ended Output Impedance Single Ended Output Impedance Matching Within a Single Lane Short Circuit Current Output Differential Swing Output Single Ended Swing Test Conditions Low = 2.0V, High = VCC + 0.5V Low = -3.0V, High = 0.8V VCC = Max., VIN = VCC VCC = Max., VIN = 0V REFCLK LVPECL-compatible Inputs VCC - 2.0 VCC - 1.45 750 -200 VCC - 0.5 VCC - 0.15 VCC - 1.2 VCC - 0.7 5 25 75 30 125 75 10 -100 100 1600 800 Transmitter Differential CML-compatible Outputs 100 differential load 100 differential load 1000 500 Notes: 5. See "Power-up Sequence Requirements" for VCCIO requirement. 6. 25 resistor terminated to termination voltage of 1.5V. Document #: 38-02021 Rev. *C Page 20 of 44 2.5-Gbps Programmable Serial Interface Parameter VICHH VICLL ZVTT LDR LCMR VRSD VRMAX VDIFFC VINSGLC Description Highest Input HIGH Voltage Lowest Input LOW Voltage VTT Impedance Differential Return Loss Common Mode Return Loss Voltage Threshold Maximum Input Voltage (p-p) Input Differential Voltage Input Single-ended Swing 50 25 10 6 20 1.6 2000 1000 1.2 30 Test Conditions Min. Max. VCC Unit V V dB dB mV V mV mV Receiver Differential CML Compatible Inputs Configuration Parameters Parameter tRECONFIG Description Reconfig pin LOW time before it goes HIGH Min. 200 Unit ns IN + V IN V D IN S G L C V D IF F C = ( IN + ) - ( IN - ) OUT+ V O UTV D SG LO C V D IF F O C = (O U T + )-(O U T -) Figure 15. Differential Parameters Waveforms Power-up Sequence Requirements * Upon power-up, all the outputs remain three-stated until all the VCC pins have powered up to the nominal voltage and the part has completed configuration. * The part will not start configuration until VCC, VDDQ, VCCIO, VCCJTAG, VCCCNFG, VCCPLL and VCEP have reached nominal voltage. * VCC pins can be powered up in any order. This includes VCC, VDDQ, VCCIO, VCCJTAG, VCCCNFG, VCCPLL and VCEP. * All VCCIOs on a bank should be tied to the same potential and powered up together. * All VCCIOs (even the unused banks) need to be powered up to at least 1.5V before configuration has completed. * Maximum ramp time for all VCCs should be 0V to nominal voltage in 100 ms. Document #: 38-02021 Rev. *C Page 21 of 44 2.5-Gbps Programmable Serial Interface Switching Characteristics Timing Parameter Values [7] Parameter Combinatorial Mode Parameters tPD tEA tER tPRR tPRO Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the horizontal or vertical channel associated with that cluster Global control to output enable Global control to output disable Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical channel associated with the cluster the macrocell is in Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel associated with the cluster that the macrocell is in to any pin output on those same channels Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in the farthest cluster on the horizontal or vertical channel the pin is associated with Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the cluster that macrocell is in Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock Clock to output of an I/O cell register to the output pin associated with that register Macrocell clock to macrocell clock through array logic within the same cluster Macrocell clock to macrocell clock through array logic in different clusters on the same channel I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster that the macrocell is in Clock to output disable (high-impedance) Clock to output enable (low-impedance) Maximum frequency with internal feedback--within the same cluster Maximum frequency with internal feedback--within different clusters at the opposite ends of a horizontal or vertical channel Set-up time for macrocell used as input register, from input to product term clock Hold time of macrocell used as an input register Product term clock to output delay from input pin Register to register delay through array logic in different clusters on the same channel using a product term clock Adder for a signal to switch from a horizontal to vertical channel and vice-versa Cluster to Cluster delay adder (through channels and channel PIM) 6.5 3.0 1.0 8.0 1.5 286 222 3.5 4.5 5.0 5.0 3.5 1.0 1.0 4.0 6.0 10 7.5 5.0 5.0 ns ns ns ns ns Description Min. Max. Unit tPRW 3.6 ns Synchronous Clocking Parameters tMCS tMCH tMCCO tIOS tIOH tIOCO tSCS tSCS2 tICS tOCS tCHZ tCLZ fMAX fMAX2 3.0 0.0 6.0 ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Product Term Clocking Parameters tMCSPT tMCHPT tMCCOPT tSCS2PT ns ns ns ns Channel Interconnect Parameters tCHSW tCL2CL 1.0 2.0 ns ns Note: 7. Add tCHSW to signals making a horizontal to vertical channel switch or vice versa. Document #: 38-02021 Rev. *C Page 22 of 44 2.5-Gbps Programmable Serial Interface Switching Characteristics Timing Parameter Values [7] (continued) Parameter Miscellaneous Parameters tCPLD tMCCD tMCCJ tDWSA tDWOSA tLOCK fPLLO fPLLI Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This parameter can be added to the tPD and tSCS parameters for each extra pass through the AND/OR array required by a given signal path Adder for carry chain logic per macrocell Maximum cycle to cycle jitter time PLL delay with skew adjustment PLL delay without any skew adjustment Lock time for the PLL Output frequency of the PLL Input frequency of the PLL 6.2 12.5 -150 -150 3.0 ns Description Min. Max. Unit 0.25 150 150 250 266 133 ns ps ns ps PLL Parameters -1.35 -0.85 s MHz MHz Cluster Memory Timing Parameter Values 200 Parameter Asynchronous Mode Parameters tCLMAA tCLMPWE tCLMSA tCLMHA tCLMSD tCLMHD Cluster memory access time. Delay from address change to read data out Write enable pulse width Address set-up to the beginning of write enable Address hold after the end of write enable with both signals from the same I/O block Data set-up to the end of write enable Data hold after the end of write enable Clock cycle time for flow-through read and write operations (from macrocell register through cluster memory back to a macrocell register in the same cluster) Clock cycle time for pipelined read and write operations (from cluster memory input register through the memory to cluster memory output register) Address, data, and WE set-up time of pin inputs, relative to a global clock Address, data, and WE hold time of pin inputs, relative to a global clock Global clock to data valid on output pins for flow through data Global clock to data valid on output pins for pipelined data Cluster memory input clock to macrocell clock in the same cluster Cluster memory output clock to macrocell clock in the same cluster Macrocell clock to cluster memory input clock in the same cluster Macrocell clock to cluster memory output clock in the same cluster Asynchronous cluster memory access time from input of cluster to output of cluster 8.0 5.0 4.0 6.5 6.0 6.0 2.0 1.0 6.0 0.5 10 5.0 3.0 0.0 11 7.5 11 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit Synchronous Mode Parameters tCLMCYC1 tCLMCYC2 tCLMS tCLMH tCLMDV1 tCLMDV2 tCLMMACS1 tCLMMACS2 tMACCLMS1 tMACCLMS2 tCLMCLAA Internal Parameters Channel Memory Timing Parameter Values Parameter Dual-Port Asynchronous Mode Parameters tCHMAA tCHMPWE tCHMSA Channel memory access time. Delay from address change to read data out Write enable pulse width Address set-up to the beginning of write enable 6.0 2.0 11 ns ns ns Description Min. Max. Unit Document #: 38-02021 Rev. *C Page 23 of 44 2.5-Gbps Programmable Serial Interface Channel Memory Timing Parameter Values (continued) tCHMHA tCHMSD tCHMHD tCHMBA Address hold after the end of write enable with both signals from the same I/O block Data set-up to the end of write enable Data hold after the end of write enable Channel memory asynchronous dual port address match (busy access time) Clock cycle time for flow through read and write operations (from macrocell register through channel memory back to a macrocell register in the same cluster) Clock cycle time for pipelined read and write operations (from channel memory input register through the memory to channel memory output register) Address, data, and WE set-up time of pin inputs, relative to a global clock Address, data, and WE hold time of pin inputs, relative to a global clock Global clock to data valid on output pins for flow through data Global clock to data valid on output pins for pipelined data Channel memory synchronous dual-port address match (busy, clock to data valid) Channel memory input clock to macrocell clock in the same cluster Channel memory output clock to macrocell clock in the same cluster Macrocell clock to channel memory input clock in the same cluster Macrocell clock to channel memory output clock in the same cluster Read and write minimum clock cycle time Data, read enable, and write enable set-up time relative to pin inputs Data, read enable, and write enable hold time relative to pin inputs Data access time to output pins from rising edge of read clock (read clock to data valid) Channel memory FIFO read clock to macrocell clock for read data Macrocell clock to channel memory FIFO write clock for write data Read or write clock to respective flag output at output pins Read or write clock to macrocell clock with FIFO flag Master Reset Pulse Width Master Reset Recovery Time Master Reset to Flag and Data Output Time Read/Write Clock Skew Time for Full Flag Read/Write Clock Skew Time for Empty Flag Read/Write Clock Skew Time for Boundary Flags Asynchronous channel memory access time from input of channel memory to output of channel memory 7.0 9 5.0 4.0 10.0 2.0 2.0 5.0 5.0 5.0 11 9.0 5.0 5.0 7.3 5.0 4.0 0.0 7.0 ns ns ns ns ns ns ns ns ns ns ns 10 5.3 3.3 0.0 11 7.5 9.0 1.0 6.0 0.5 9.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Dual-Port Synchronous Mode Parameters tCHMCYC1 tCHMCYC2 tCHMS tCHMH tCHMDV1 tCHMDV2 tCHMBDV tCHMMACS1 tCHMMACS2 tMACCHMS1 tMACCHMS2 tCHMCLK tCHMFS tCHMFH tCHMFRDV tCHMMACS tMACCHMS tCHMFO tCHMMACF tCHMFRS tCHMFRSR tCHMFRSF tCHMSKEW1 tCHMSKEW2 tCHMSKEW3 tCHMCHAA Synchronous FIFO Data Parameters Synchronous FIFO Flag Parameters Internal Parameters High-speed PSI Transceiver Timing Parameter Values Parameter Transceiver Interfacing Timing Parameters tTS tTXCLK tRS tRXCLK TXCLK Frequency (must be frequency coherent to REFCLK) TXCLK Period RXCLK Frequency RXCLK Period 154.5 6.38 154.5 6.38 156.5 6.47 156.5 6.47 MHz ns MHz ns Description Min. Max. Unit Document #: 38-02021 Rev. *C Page 24 of 44 2.5-Gbps Programmable Serial Interface High-speed PSI Transceiver Timing Parameter Values Parameter REFCLK Timing Parameters tREF tREFP tREFD tREFT tREFR tREFF tREFJ CML Serial Outputs tDRF tUID[9] CML Serial Outputs tRISE tFALL CML Output Rise Time (20-80%, 100 balanced load) CML Output Fall Time (80-20%, 100 balanced load) 60 60 170 170 ps ps Driver Rise/Fall Time (20-80% rise, 80-20% fall, 100 balanced load) Unit Interval 100 400 400 ps ps REFCLK Input Frequency REFCLK Period REFCLK Duty Cycle REFCLK Frequency Tolerance (relative to received serial data) REFCLK Rise Time REFCLK Fall Time REFCLK Jitter [8] Description Min. 154.5 6.38 35 -100 0.3 0.3 Max. 156.5 6.47 65 +100 1.5 1.5 Unit MHz ns % ppm ns ns See Figure 16 for phase noise requirements Jitter Specifications for CYP25G01K100 (Non-SONET) tEYE tJDR tJTR tJD tJT Eye opening at CML serial inputs Deterministic Jitter allowed at CML serial inputs Total Jitter allowed at CML serial inputs Deterministic Jitter at CML serial outputs Total Jitter at CML serial outputs 140 0.41 0.65 0.17 0.35 ps UI UI UI UI Jitter Specifications for CYS25G01K100 (SONET) Parameter tTJ-TXPLL tTJ-RXPLL Description Total Output Jitter for TX PLL (p-p)[10] [10] Min. Typical[11] 0.03 0.007 0.035 0.008 Max.[11] 0.04 0.008 0.05 0.01 Unit UI UI UI UI Total Output Jitter for TX PLL (rms)[10] Total Output Jitter for RX CDR PLL (p-p) Total Output Jitter for RX CDR PLL (rms)[10] Note: 8. 20 ppm is required to meet SONET output frequency specification. 9. Measured with serial bit rate of 2.5 Gbps. 10. The RMS and P-to-P jitter values are measured using a 12 KHz to 20 MHz SONET filter. 11. Typical at room temperature, Max. at 0o deg C. Document #: 38-02021 Rev. *C Page 25 of 44 2.5-Gbps Programmable Serial Interface Phase Noise Limits for CYS25G01K100(SONET) REFCLK Source CYS25G0101DX Reference Clock Phase Noise Limits -75 -85 -95 Phase Noise (dBc) -105 -115 -125 -135 -145 -155 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 Frequency (Hz) Figure 16. Phase Noise Limits for REFCLK Inputs of CYS25G01K100 Jitter Transfer for CYS25G01K100 (SONET) RXPLL Figure 17. Jitter Transfer for CYS25G01K100 Jitter Tolerance for CYS25G01K100 (SONET) Figure 18. Jitter Tolerance for CYS25G01K100 Document #: 38-02021 Rev. *C Page 26 of 44 2.5-Gbps Programmable Serial Interface Input and Output Standard Timing Delay Adjustments All the timing specifications in this data sheet are specified based on 3.3V PCI compliant inputs and outputs (fast slew Input/Output Standard LVTTL - 2 mA LVTTL - 4 mA LVTTL - 6 mA LVTTL - 8 mA LVTTL - 12 mA LVTTL - 16 mA LVTTL - 24 mA LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V PCI GTL+ SSTL3 I SSTL3 II SSTL2 I SSTL2 II HSTL I HSTL II HSTL III HSTL IV Output Delay Adjustments (ns) tIOD 2.75 1.8 1.8 1.2 0.6 0.16 0 0 0.14 0.41 1.6 -0.14 0.02 [13] rates[12]). Apply following adjustments if the inputs and outputs are configured to operate at other standards. Input Delay Adjustments(ns) tIOIN 0 0 0 0 0 0 0 0 0.1 0.2 0.5 0 0.5 0.5 0.5 0.9 0.9 0.5 0.5 0.5 0.5 tCKIN 0 0 0 0 0 0 0 0 0.1 0.2 0.4 0 0.4 0.3 0.3 0.5 0.5 0.5 0.5 0.5 0.5 tIOREGPIN 0 0 0 0 0 0 0 0 0.2 0.4 0.3 0 0.2 0.3 0.3 0.6 0.6 0.3 0.3 0.3 0.3 tEA 0 0 0 0 0 0 0 0 0.05 0.1 0.7 0 0.6[13] 0.3 0.2 0.4 0.2 0.9 0.8 0.5 0.6 tER 0 0 0 0 0 0 0 0 0 0 0.1 0 0.9[13] 0.1 0 0 0 0.5 0.5 0.1 0 -0.15 -0.4 -0.02 -0.22 0.94 0.79 0.77 0.44 Notes: 12. For "slow slew rate" output delay adjustments, refer to Warp software's static timing analyzer results. 13. These delays are based on falling edge output. The rising edge delay depends on the size of pull up resistor and termination voltage. Switching Waveforms General Switching Waveforms Combinatorial Output INPUT tPD COMBINATORIAL OUTPUT Document #: 38-02021 Rev. *C Page 27 of 44 2.5-Gbps Programmable Serial Interface Switching Waveforms (continued) Registered Output with Synchronous Clocking (Macrocell) INPUT tMCS SYNCHRONOUS CLOCK tMCH REGISTERED OUTPUT tMCCO Registered Input in I/O Cell DATA INPUT tIOS tIOH INPUT REGISTER CLOCK tIOCO REGISTERED OUTPUT Clock to Clock INPUT REGISTER CLOCK tICS tSCS MACROCELL REGISTER CLOCK PT Clock to PT Clock DATA INPUT tMCSPT PT CLOCK tSCS2PT Asynchronous Reset/Preset RESET/PRESET INPUT tPRO REGISTERED OUTPUT tPRW tPRR CLOCK Document #: 38-02021 Rev. *C Page 28 of 44 2.5-Gbps Programmable Serial Interface Switching Waveforms (continued) Output Enable/Disable GLOBAL CONTROL INPUT tER OUTPUTS tEA Cluster Memory Asynchronous Timing READ WRITE READ ADDRESS (AT THE CLUSTER INPUT) WRITE ENABLE tCLMPWE INPUT tCLMCLAA tCLMCLAA OUTPUT Cluster Memory Asynchronous Timing 2 READ ADDRESS (AT THE I/O PIN) tCLMSA tCLMHA WRITE READ WRITE ENABLE tCLMPWE INPUT tCLMSD tCLMAA tCLMHD tCLMAA OUTPUT Document #: 38-02021 Rev. *C Page 29 of 44 2.5-Gbps Programmable Serial Interface Switching Waveforms (continued) Cluster Memory Synchronous Timing READ WRITE READ GLOBAL CLOCK tCLMS tCLMH tCLMCYC1 ADDRESS tCLMS tCLMH tCLMS tCLMH WRITE ENABLE REGISTERED INPUT tCLMDV1 tCLMDV1 tCLMDV1 REGISTERED OUTPUT Cluster Memory Internal Clocking MACROCELL INPUT CLOCK tCLMMACS1 tMACCLMS1 CLUSTER MEMORY INPUT CLOCK tCLMMACS2 tMACCLMS2 CLUSTER MEMORY OUTPUT CLOCK Document #: 38-02021 Rev. *C Page 30 of 44 2.5-Gbps Programmable Serial Interface Switching Waveforms (continued) Cluster Memory Output Register Timing (Asynchronous Inputs) ADDRESS WRITE ENABLE INPUT tCLMCYC2 GLOBAL CLOCK (OUTPUT REGISTER) tCLMDV2 EGISTERED OUTPUT Cluster Memory Output Register Timing (Synchronous Inputs) ADDRESS WRITE ENABLE INPUT tCLMCYC2 GLOBAL CLOCK (INPUT REGISTER) tCLMS tCLMH GLOBAL CLOCK (OUTPUT REGISTER) tCLMDV2 REGISTERED OUTPUT Document #: 38-02021 Rev. *C Page 31 of 44 2.5-Gbps Programmable Serial Interface Switching Waveforms (continued) Channel Memory DP Asynchronous Timing ADDRESS An-1 An An+1 An+2 tCHMSA tCHMPWE tCHMHA WRITE ENABLE tCHMSD tCHMHD DATA INPUT Dn tCHMAA tCHMAA OUTPUT Dn-1 Dn Dn+1 Channel Memory Internal Clocking MACROCELL INPUT CLOCK tMACCHMS1 tCHMMACS1 CHANNEL MEMORY INPUT CLOCK tCHMMACS2 tMACCHMS2 CHANNEL MEMORY OUTPUT CLOCK Document #: 38-02021 Rev. *C Page 32 of 44 2.5-Gbps Programmable Serial Interface Switching Waveforms (continued) Channel Memory Internal Clocking 2 MACROCELL INPUT CLOCK tCHMMACS FIFO READ CLOCK tMACCHMS FIFO WRITE CLOCK tCHMMACF FIFO READ OR WRITE CLOCK Channel Memory DP SRAM Flow Through R/W Timing CLOCK tCHMCYC1 tCHMS tCHMH ADDRESS An-1 An An+1 An+2 An+3 WRITE ENABLE tCHMS tCHMH DATA INPUT Dn-1 Dn+1 Dn+3 tCHMDV1 tCHMDV1 tCHMDV1 tCHMDV1 OUTPUT Dn-1 Dn Dn+1 Dn+2 Dn+3 Document #: 38-02021 Rev. *C Page 33 of 44 2.5-Gbps Programmable Serial Interface Switching Waveforms (continued) Channel Memory DP SRAM Pipeline R/W Timing CLOCK tCHMCYC2 tCHMS tCHMH ADDRESS An-1 An tCHMH An+1 An+2 An+3 tCHMS WRITE ENABLE tCHMS tCHMH DATA INPUT Dn-1 Dn+1 Dn+3 tCHMDV2 tCHMDV2 tCHMDV2 OUTPUT Dn-1 Dn Dn+1 Dn+2 Dual-Port Asynchronous Address Match Busy Signal ADDRESS A Bn An ADDRESS B An-1 An An+1 tCHMBA tCHMBA ADDRESS MATCH Document #: 38-02021 Rev. *C Page 34 of 44 2.5-Gbps Programmable Serial Interface Switching Waveforms (continued) Dual-Port Synchronous Address Match Busy Signal CLOCK ADDRESS A An-1 An ADDRESS B Bn-1 tCHMS An tCHMS Bn+1 ADDRESS MATCH tCHMBDV tCHMBDV Channel Memory Synchronous FIFO Empty/Write Timing PORT B CLOCK tCHMCLK tCHMFS tCHMFH WRITE ENABLE REGISTERED INPUT Dn+1 EMPTY FLAG (active low) tCHMSKEW2 tCHMFO tCHMFO PORT A CLOCK READ ENABLE tCHMFRDV REGISTERED OUTPUT Document #: 38-02021 Rev. *C Page 35 of 44 2.5-Gbps Programmable Serial Interface Switching Waveforms (continued) Channel Memory Synchronous FIFO Full/Read Timing PORT A CLOCK tCHMCLK tCHMFS tCHMFH READ ENABLE tCHMFRDV REGISTERED OUTPUT FULL FLAG (active low) tCHMSKEW1 tCHMFO tCHMFO PORT B CLOCK WRITE ENABLE tCHMS tCHMH REGISTERED INPUT Channel Memory Synchronous FIFO Programmable Flag Timing PORT B CLOCK tCHMCLK tCHMFH tCHMFS WRITE ENABLE PROGRAMMABLE ALMOST-EMPTY FLAG (active LOW) tCHMSKEW3 tCHMFO tCHMFO PORT A CLOCK tCHMFS READ ENABLE tCHMFH Document #: 38-02021 Rev. *C Page 36 of 44 2.5-Gbps Programmable Serial Interface Switching Waveforms (continued) PORT B CLOCK tCHMCLK WRITE ENABLE tCHMFO PROGRAMMABLE ALMOST-FULL FLAG (active LOW) tCHMFO tCHMSKEW3 PORT A CLOCK READ ENABLE Channel Memory Synchronous FIFO Master Reset Timing tCHMFRS MASTER RESET INPUT tCHMFRSR READ ENABLE / WRITE ENABLE tCHMFRSF EMPTY/FULL PROGRAMMABLE ALMOST EMPTY FLAGS HALF-FULL/ PROGRAMMABLE ALMOST FULL FLAGS REGISTERED OUTPUT tCHMFRSF tCHMFRSF Optical Module or Limiting Amplifier OUT+ 0.1 F IN+ 50 ohms CYS25G01K100 0.1 F 50 ohms OUTIN- 100 ohms Figure 19. Serial Input Termination Document #: 38-02021 Rev. *C Page 37 of 44 2.5-Gbps Programmable Serial Interface 0.1 F 50 ohms 100 50 ohms OUT- OUT+ CYS25G01K100 0.1 F Internally source matched to drive 100 differential Transmission Lines Figure 20. Serial Output Termination VC C =3.3V LV PE C L C lock S ource C LKO U T + 50 ohm s 82.5 V C C =3.3V C LKO U T 50 ohm s 82.5 130 R E FC LK 130 C YS 25G 01K 100 R EF C LK+ Figure 21. REFCLK Oscillator Termination VC C =3.3V LV PE C L C lock S ource C LKO U T + 50 ohm s 82.5 V C C =3.3V C LKO U T 50 ohm s 82.5 130 0.01 F R E FC LK 130 0.01 F C YS 25G 01K 100 R EF C LK+ Figure 22. AC-Coupled REFCLK Oscillator Termination Pin and Signal Description Name CCLK CDONE CDATA GCLK0-1 CCE GCTL0-3 IO/VREF0 IO/VREF1 IO/VREF2 IO/VREF3 IO/VREF4 IO/VREF5 Function Output Output Input Input Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Signal Description Configuration Clock for serial interface with the external boot PROM Flag indicating that configuration is complete Pin to receive configuration data from the external boot PROM Global Input Clock signals 0 through 1. Other global clocks are TXCLK and RXCLK. Chip select for the external boot PROM Global Control signals 0 through 3 Dual function pin: I/O or Reference Voltage for Bank 0 Dual function pin: I/O or Reference Voltage for Bank 1 Dual function pin: I/O or Reference Voltage for Bank 2 Dual function pin: I/O or Reference Voltage for Bank 3 Dual function pin: I/O or Reference Voltage for Bank 4 Dual function pin: I/O or Reference Voltage for Bank 5 Page 38 of 44 Standard Device Signals Document #: 38-02021 Rev. *C 2.5-Gbps Programmable Serial Interface Pin and Signal Description (continued) Name IO IO6/Lock HSTLREF MSEL Reconfig CRST TCK TDI TDO TMS TXD[15:0] TXCLK Function Input/Output Input/Output Input Input Input Output Input Input Output Input Internal Internal Input or Output pin Dual function pin: I/O in Bank 6 or PLL lock output signal Reference Voltage for HSTL Specific IO Banks Mode Select Pin Pin to start configuration of PSI Reset signal to interface with the external boot PROM JTAG Test Clock JTAG Test Data In JTAG Test Data Out JTAG Test Mode Select Parallel Transmit Data Inputs to the serial transceiver block. A 16-bit word, sampled by TXCLK. TXD[15] is the most significant bit (the first bit transmitted) Parallel Transmit Data Input Clock to the serial transceiver block. Divide by 16 of the selected transmit bit-rate clock. One of the four global clocks in the programmable logic. Parallel Receive Data Output from the serial transceiver block. These outputs change following RXCLK. RXD[15] is the most significant bit of the output word, and is received first on the serial interface Receive Clock Output from the serial transceiver block. Divide by 16 of the bit-rate clock extracted from the received serial stream. One of the four global clocks in the programmable. Common Mode Termination. Capacitor (0.1 F) shunt to VSS for common mode noise Receive Loop Filter Capacitor (Negative) Receive Loop Filter Capacitor (Negative) Receive Loop Filter Capacitor (Positive) Receive Loop Filter Capacitor (Positive) Signal Description Transmit Path Signals Receive Path Signals RXD[15:0] Internal RXCLK Internal CMSER RXCN1 RXCN2 RXCP1 RXCP2 REFCLK Analog Analog Analog Analog Analog Transceiver Control and Status Signals Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and input receive PLLs. A derivative of this input clock may also be used to clock the transmit parallel interface Internal Line Fault Indicator Output Signal. When LOW, this signal indicates that the selected receive data stream has been detected as invalid by either a LOW input on SD, or by the receive VCO being operated outside its specified limits Reset for all logic functions in the serial transceiver block except the transmit FIFO Receive PLL Lock to Reference Input Signal. When LOW, the receive PLL locks to REFCLK instead of the received serial data stream Signal Detect. When LOW, the receive PLL locks to REFCLK instead of the received serial data stream Transmit FIFO Error Output Signal. When HIGH the transmit FIFO has either under or overflowed. The FIFO must be reset to clear the error indication Transmit FIFO Reset Input Signal. When LOW, the in and out pointers of the transmit FIFO are set to maximum separation Device Power Down Input Signal. When LOW, the logic and drivers are all disabled and placed into a standby condition where only minimal power is dissipated LFI RESET LOCKREF SD FIFO_ERR FIFO_RST PWRDN Internal Internal LVTTL input Internal Internal Internal Document #: 38-02021 Rev. *C Page 39 of 44 2.5-Gbps Programmable Serial Interface Pin and Signal Description (continued) Name DIAGLOOP Function Internal Signal Description Diagnostic Loopback Control Input Signal. When HIGH, transmit data is routed through the receive clock and data recovery and presented at the RXD[15:0] outputs. When LOW, received serial data is routed through the receive clock and data recovery and presented at the RXD[15:0] outputs Line Loopback Control Input Signal. When HIGH, received serial data is looped back from receive to transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data passed to the OUT line driver is controlled by LOOPA. When both LINELOOP and LOOPA are LOW, the data passed to the OUT line driver is generated in the transmit shifter Analog Line Loopback Input Signal. When LINELOOP is LOW and LOOPA is HIGH, received serial data is looped back from receive input buffer to transmit output buffer, but is not routed through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the OUT line driver is controlled by LINELOOP Loop Time Mode Input Signal. When HIGH, the extracted receive bit-clock replaces transmit bit-clock. When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock Differential Serial Data Output. This differential CML output (+3.3V referenced) is capable of driving terminated 50 transmission lines or commercial fiberoptic transmitter modules Differential Serial Data Input. This differential input accept the serial data stream for deserialization and clock extraction +3.3V Supply (operating voltage) Signal and Power Ground +3.3V Quiet Power Quiet Ground +1.5V Supply for HSTL Outputs Power Power Power Power Power Power Power Power Power Ground Power VCC for I/O bank 0 VCC for I/O bank 1 VCC for I/O bank 2 VCC for I/O bank 3 VCC for I/O bank 4 VCC for I/O bank 5 VCC for JTAG pins VCC for Configuration port VCC for logic PLL Ground for logic PLL VCC for the Self-BootTM solution embedded boot PROM Transceiver Loop Control Signals LINELOOP Internal LOOPA Internal LOOPTIME Internal Serial I/O OUT Differential CML output Differential CML input Power Ground IN Power VCC GND VCCQ VSSQ VDDQ VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCJTAG VCCCFG VCCPLL GNPLL VCEP Document #: 38-02021 Rev. *C Page 40 of 44 2.5-Gbps Programmable Serial Interface Pin Configurations 456-ball BGA (25G01K100): Top View 1 2 REF 3 IO7 IO7 IO7 IO0 IO0 IO0 4 IO7 HSTLREF IO7 IO7 GCTL0 VCC 5 IO7 IO7 VDDQ VDDQ GND GND 6 IO7 IO7 VCC VDDQ GND 7 HSTLREF IO7 VCC VDDQ IO7 8 IO7 VDDQ IO7 9 IO7 IO7 GCTL 3 10 IO7 HSTLREF IO7 IO7 HSTLREF 11 HSTLREF IO6 VDDQ NC IO6 12 HSTLREF IO6 VDDQ VDDQ IO6 13 IO6 IO6 VDDQ VCC IO6 14 IO6 IO6 HSTLREF IO6 IO6/ Lock 15 IO6 IO6 IO6 IO6 IO6 16 HSTLREF IO6 IO6 IO6 IO6 17 IO5 IO5 IO5 18 IO5 IO5 IO5 19 IO5 IO5 IO5 20 IO/VRE F5 IO5 21 IO5 IO5 22 IO5 IO/VRE F5 IO5 NC IO5 NC NC NC NC VSSQ 23 IO5 IO5 IO5 GCLK1 24 IO/VRE F5 IO5 IO5 IO5 25 IO5 IO5 TDO TMS 26 GND IO5 TCK TDI A GND HSTLB HSTL- HSTLREF REF IO7 IO0 IO0 IO0 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF C IO0 D IO0 E IO0 F IO/VR EF0 GCTL2 GCTL1 VDDQ IO5 VCC IO5 GND HSTLREF GND GND VCCPL VDDQ VDDQ L IO/VRE F5 IO5 IO5 VCCIO5 VCCIO5 VCCIO VCCJT 5 AG NC NC VSSQ VSSQ VSSQ NC NC NC VSSQ NC NC NC NC NC NC NC NC NC G IO0 IO/VRE VCC VCCIO0 GCLK0 F0 H IO0 J IO0 IO0 IO0 IO0 IO0 VCC VCCIO0 GND VCC VCCIO0 GND IO0 IO0 IO0 IO0 IO1 IO1 IO1 IO1 IO/VRE F1 IO1 VCEP IO0 GND GND GND IO1 VCC IO0 IO0 IO/VRE F0 IO0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GNPLL GND GND GND GND GND GND GND GND GND GND VSSQ VSSQ VSSQ NC NC NC K IO0 L IO0 NC SD NC NC NC VSSQ NC M IO0 IO/VRE F0 RXCN1 RXCP1 RXCN2 RXCP2 VCCQ VSSQ VSSQ VSSQ VCCQ VCCQ VCCQ VCCQ VSSQ IN+ IN- N VCC P IO1 R IO1 IO0 IO1 IO1 VCCIO1 GND IO1 GND IO1 IO1 IO1 IO1 GND GND GND IO1 GND IO2 GND GND GND IO2 IO/VRE F2 NC VSSQ VSSQ CMSE R VSSQ OUT+ OUTVCCQ VCCQ VCCQ IO4 IO4 IO4 IO4 IO4 IO4 IO4 IO4 IO4 IO4 IO4 IO3 IO/VRE F3 IO3 VCCIO 4 IO4 IO/VRE F4 IO4 IO4 IO4 IO3 IO3 GND T IO/VR IO/VRE EF1 F1 IO1 IO1 IO1 IO1 IO1 U IO1 V IO1 W IO1 Y IO1 AA IO1 REF- VCCIO4 CLK+ REF- VCCIO4 CLKIO4 IO4 IO2 IO2 IO2 IO/VRE F2 IO2 IO2 IO2 IO2 IO2 IO2 IO3 IO2 IO/VRE F2 IO2 VCC IO3 GND IO3 GND IO3 IO3 IO3 IO/VRE F3 GND IO3 IO3 IO3 IO3 GND IO/VRE F3 IO3 IO3 IO3 IO3 NC IO3 NC IO3 VCEP NC IO4 VCCIO1 IO/VRE F1 AB GND CDONE VCCIO1 IO1 AC CDAT RECON A FIG IO2 IO2 IO2 IO2 IO2 IO2 VCCCF VCCIO2 VCCIO2 VCCIO2 VCCIO G 2 IO2 IO/VRE F2 IO2 IO2 IO2 IO2 IO2 IO2 IO/VRE F2 NC IO2 IO2 VDDQ VCCIO VCCIO 3 3 IO2 IO2 IO/VRE F3 IO3 IO3 IO3 IO3 IO3 IO3 VCCIO4 IO/VRE IO/VRE F4 F4 IO3 IO3 IO3 AD CRST CCLK VDDQ VDDQ IO2 IO2 IO2 IO2 VCC VCCIO3 VCCIO3 IO/VRE F3 IO3 IO3 IO/VRE F3 IO3 IO3 IO3 IO3 IO3 AE CCE MSEL IO/VRE F2 AF GND 1 IO2 IO2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Document #: 38-02021 Rev. *C Page 41 of 44 2.5-Gbps Programmable Serial Interface CY P 25G 01 K100 V 1 - MG C Standard Cypress Designator P = PHY S = SONET PHY 15 = 1.5Gbps 25 = 2.5Gbps C = Commercial I = Industrial MG = Package Type 01 = 1 channel V = Standard Power 3.3V-Vcc K100 = 100K gates Ordering Information Device 25G01K100 Channels and Link Speed 1 x 2.5 Gbps 1 x 2.5 Gbps Ordering Code CYP25G01K100V1-MGC CYS25G01K100V1-MGC Package Name Package Type Operating Range Commercial 456MGC 456-ball Ball Grid Array 456MGC 456-ball Ball Grid Array Document #: 38-02021 Rev. *C Page 42 of 44 2.5-Gbps Programmable Serial Interface Package Diagram 456-ball Ball Grid Array (35 x 35 x 2.33 mm) BG456 51-85133-*A ZBT is a trademark of IDT. InfiniBand is a trademark of the InfiniBand Trade Association. QDR is a trademark of Micron, IDT, and Cypress Semiconductor Corporation. Windows is a registered trademark of Microsoft Corporation. SpeedWave and ViewDraw are trademarks of ViewLogic. Warp is a registered trademark, and NoBL, Programmable Interconnect Matrix, PIM, Spread Aware, AnyVolt, Self-Boot, In-System Reprogrammable, ISR, Programmable Serial Interface, and PSI are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-02021 Rev. *C Page 43 of 44 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 2.5-Gbps Programmable Serial Interface Document History Page Document Title: 2.5-Gbps Programmable Serial Interface Document Number: 38-02021 REV. ** *A *B *C ECN NO. 106745 107726 109064 120882 Orig. of Issue Date Change 05/25/01 06/04/01 09/07/01 12/13/02 SZV MHW MHW PDS Description of Change Change from Spec #38-01093 to 38-02021 Updated Marketing Part Numbers Added x8 feature in PLL and CHAR data Revised data sheet to reflect only 2.5-Gbps single channel 100K programmable logic PSI data. Added SONET jitter specs and jitter performance data for CYS25G01K100. Added REFCLK phase noise limits plot for CYS25G01K100. Changed title. Updated logic PLL data with additional multiplication factors available. Added sections titled "Registering TXD[15:0] Data Before it enters Serial Transceiver Block" and "Registering RXD[15:0] Data before it enters Programmable LB" under the major section called "Serial Transceiver Operation." Updated some Timing Parameter Values. Updated Output Differential Swing and Input Differential Voltage. Document #: 38-02021 Rev. *C Page 44 of 44 |
Price & Availability of CYP25G01K100
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |